MIPS on FLEET Update

The FLEET computer [1] is a new architecture designed from the ground up with parallelism in mind, providing the programmer with direct control over data movement and concurrency. Since FLEET is a completely new architecture, programming for it can be quite challenging. The machine is inherently parallel, so sequential programming techniques do not directly translate to it. The MIPS to FLEET translator [2] addresses this issue by providing a mechanism for running sequential code on FLEET. Since the MIPS translator was written, FLEET has undergone many revisions, so the translator is not compatible with the current version of FLEET, which is very close to the eventual FLEET 3 hardware implementation. In this report, I discuss the changes necessary to achieve this compatibility. Though the new translator design is close to complete, the implementation still needs significant work before it is finished. While the MIPS translator allows sequential code to be run on FLEET, it takes little advantage of FLEET’s parallelism. In this report, I also discuss one possible scheme for parallelizing the output of the translator.